1. Field of the Invention
The present invention is related to a lithography system and a semiconductor processing process, and more particularly, to a lithography system and a semiconductor processing process, containing performing at least one re-correct process.
2. Description of the Prior Art
With decreasing feature sizes and shrinking line widths of integrated circuits, lithography has become critical for semiconductor manufacture. As the tolerance of line width error is increasingly small, lithography machines have been upgraded from step-and-repeat systems (steppers) to advanced step-and-scan systems (scanners). To enhance the resolution and alignment accuracy in lithography, it is necessary to control the overlay errors of lithography to within a tolerance.
A semiconductor process refers to a process used to create a large number of semiconductor devices on a wafer using a multiple-step sequence of photolithographic and chemical processing steps. In such a highly-laminating process, when one of laminated layers is misaligned, the subsequent layers may thus be affected and further misaligned, thereby leading to failure of electrical connections among semiconductor devices and the layers, function losses, or short circuits. Therefore, precise and stable overlay control is a relatively important factor for process management to ensure yield of the semiconductor devices and efficiency of production.
For example, a conventional step-and-repeat aligner (i.e., a stepper or scanner) usually has an alignment sensor for detecting alignment marks that are disposed at specific locations of a wafer before a lithography exposure process, and an alignment offset of the aligner may be calculated according to the detected misalignment/alignment. If a subsequent rework process is required for the wafer, the overlay offset may be used to calibrate the aligner for ensuring optimal alignment between patterns of a current patterning layer (or an upper layer) and a previous patterning layer (or a lower layer).